1. Field of the Invention
This technology relates to high density memory devices with decoding structures in the z-direction, or depth direction. Such decoding distinguishes between different levels, or layers, of memory cells arranged to provide a three-dimensional memory array.
2. Description of Related Art
In Patent Application Publication 2010/0226195, a three dimensional memory array has the decoding function for the z-direction, or depth direction, removed from the actual array. In one example, a word line-like structure electrically connects the gates of only transistors that are in a same level of the three dimensional memory array, and are electrically disconnected from the gates transistors that are in a different level of the three dimensional memory array. In another example, the ends of NAND strings on a same level of the three dimensional memory array are electrically connected together, and are electrically disconnected from the ends of NAND strings on that are in a different level of the three dimensional memory array. Neither of these examples performs decoding of the level at the three dimensional memory array. Instead, actual decoding is performed in remotely located circuitry that then determines which level of NAND strings is selected for a particular operation. Complexity results from the structures and interconnects which connect the decoded level signals to the different levels of the three dimensional memory array.